Reading memory cells using multiple thresholds

ABSTRACT

A method for operating a memory ( 28 ) includes storing data, which is encoded with an Error Correction Code (ECC), in analog memory cells ( 32 ) of the memory by writing respective analog input values selected from a set of nominal values to the analog memory cells. The stored data is read by performing multiple read operations that compare analog output values of the analog memory cells to different, respective read thresholds so as to produce multiple comparison results for each of the analog memory cells. At least two of the read thresholds are positioned between a pair of the nominal values that are adjacent to one another in the set of the nominal values. Soft metrics are computed responsively to the multiple comparison results. The ECC is decoded using the soft metrics, so as to extract the data stored in the analog memory cells.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is an application for reissue of U.S. Pat. No.8,145,984 B2, which is a continuation of U.S. patent application Ser.No. 11/995,814 filed on Jan. 15, 2008, which is the national stage entryof PCT/IL2007/001315 filed on Oct. 30, 2007, which claims the benefit ofU.S. Provisional Patent Application 60/863,506, filed Oct. 30, 2006,U.S. Provisional Patent Application 60/867,399, filed Nov. 28, 2006,U.S. Provisional Patent Application 60/888,828, filed Feb. 8, 2007, U.S.Provisional Patent Application 60/889,277, filed Feb. 11, 2007, U.S.Provisional Patent Application 60/892,869, filed Mar. 4, 2007, U.S.Provisional Patent Application 60/894,456, filed Mar. 13, 2007, U.S.Provisional Patent Application 60/917,653, filed May 12, 2007, U.S.Provisional Patent Application 60/950,884, filed Jul. 20, 2007, and U.S.Provisional Patent Application 60/951,215, filed Jul. 22, 2007. Thedisclosures of all these related applications are incorporated herein byreference.

FIELD OF THE INVENTION

The present invention relates generally to memory devices, andparticularly to methods and systems for reading data from memory cells.

BACKGROUND OF THE INVENTION

Several types of memory devices, such as Flash memories, use arrays ofanalog memory cells for storing data. Each analog memory cell stores aquantity of an analog value, such as an electrical charge or voltage,which represents the information stored in the cell. In Flash memories,for example, each analog memory cell holds a certain amount ofelectrical charge. The range of possible analog values is typicallydivided into regions, each region corresponding to one or more data bitvalues. Data is written to an analog memory cell by writing a nominalanalog value that corresponds to the desired bit or bits. The possiblebit values that can be stored in an analog memory cell are also referredto as the memory states of the cell.

Some memory devices, commonly referred to as Single-Level Cell (SLC)devices, store a single bit of information in each memory cell, i.e.,each memory cell can be programmed to assume two possible memory states.Higher-density devices, often referred to as Multi-Level Cell (MLC)devices, store two or more bits per memory cell, i.e., can be programmedto assume more than two possible memory states.

Flash memory devices are described, for example, by Bez et al., in“Introduction to Flash Memory,” Proceedings of the IEEE, volume 91,number 4, April, 2003, pages 489-502, which is incorporated herein byreference. Multi-level Flash cells and devices are described, forexample, by Eitan et al., in “Multilevel Flash Cells and theirTrade-Offs,” Proceedings of the 1996 IEEE International Electron DevicesMeeting (IEDM), New York, N.Y., pages 169-172, which is incorporatedherein by reference. The paper compares several kinds of multilevelFlash cells, such as common ground, DINOR, AND, NOR and NAND cells.

Eitan et al., describe another type of analog memory cell called NitrideRead Only Memory (NROM) in “Can NROM, a 2-bit, Trapping Storage NVMCell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the1999 International Conference on Solid State Devices and Materials(SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which isincorporated herein by reference. NROM cells are also described byMaayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/sData Rate”, Proceedings of the 2002 IEEE International Solid-StateCircuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002,pages 100-101, which is incorporated herein by reference. Otherexemplary types of analog memory cells are Floating Gate (FG) cells,Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge TrapFlash (CTF) and phase change RAM (PRAM, also referred to as Phase ChangeMemory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example,by Kim and Koh in “Future Memory Technology including Emerging NewMemories,” Proceedings of the 24th International Conference onMicroelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004,volume 1, pages 377-384, which is incorporated herein by reference.

The analog values read from analog memory cells are sometimes distorted.The distortion may be due to various reasons, such as electrical fieldcoupling from neighboring memory cells, disturb noise caused by memoryaccess operations on other cells in the array and threshold voltagedrift caused by device aging. Some common distortion mechanisms aredescribed in the article by Bez et al., cited above. Distortion effectsare also described by Lee et al., in “Effects of Floating GateInterference on NAND Flash Memory Cell Operation,” IEEE Electron DeviceLetters, (23:5), May, 2002, pages 264-266, which is incorporated hereinby reference.

Reading data from analog memory cells often involves comparing theanalog values stored in the cells to one or more thresholds, orreference levels. Several methods for determining the appropriatethreshold values are known in the art. For example, U.S. Pat. No.5,657,332, whose disclosure is incorporated herein by reference,describes methods for recovering from hard errors in a solid-statememory system. Hard errors may arise from cells whose threshold voltagesdrifted from their intended level to cause read errors. The memorysystem includes an array of memory cells, each cell capable of havingits threshold voltage programmed or erased to an intended level. Anerror checking scheme is provided for each of a plurality of groups ofcells for identifying read errors therein. A read reference level isadjusted before each read operation on the individual group of cellscontaining read errors, each time the read reference level beingdisplaced a predetermined step from a reference level for normal read,until the error checking means no longer indicates read errors. Thedrifted threshold voltage of each cell associated with a read error isre-written to its intended level.

U.S. Pat. No. 7,023,735, whose disclosure is incorporated herein byreference, describes methods for reading Flash memory cells, which, inaddition to comparing the threshold voltages of Flash cells to integralreference voltages, compare the threshold voltages to fractionalreference voltages.

U.S. Patent Application Publication 2007/0091677, whose disclosure isincorporated herein by reference, describes methods, devices andcomputer readable code for reading data from one or more flash memorycells, and for recovering from read errors. In some embodiments, in theevent of an error correction failure by an error detection andcorrection module, the flash memory cells are re-read at least onceusing one or more modified reference voltages, until successful errorcorrection may be carried out. In some embodiments, after successfulerror correction, a subsequent read request is handled withoutre-writing data to the flash memory cells in the interim.

U.S. Pat. No. 6,963,505, whose disclosure is incorporated herein byreference, describes a method, circuit and system for determining areference voltage. In some embodiments a set of operating referencecells is established to be used in operating cells in a Non-VolatileMemory (NVM) block or array. At least a subset of cells of the NVM blockor array may be read using each of two or more sets of test referencecells, where each set of test reference cells may generate or otherwiseprovide reference voltages at least slightly offset from each other setof test reference cells. For each set of test reference cells used toread at least a subset of the NVM block, a read error rate may becalculated or otherwise determined. A set of test reference cellsassociated with a relatively low read error rate may be selected as theset of operating reference cells to be used in operating other cells,outside the subset of cells, in the NVM block or array.

U.S. Pat. No. 7,196,928 and U.S. patent Application Publications2006/0221692, 2007/0103986, 2007/0109845 and 2007/0109849, whosedisclosures are incorporated herein by reference, describe severalprocesses for reading a memory cell, which take into account theprogrammed state of an adjacent memory cell.

Some known methods use information regarding the quality of stored datawhen reading the data from memory cells. For example, U.S. Pat. No.6,751,766, whose disclosure is incorporated herein by reference,describes several methods for assessing the quality of data stored in amemory system, and for operating the memory system according to theassessed quality. The data quality is sometimes assessed during readoperations. Subsequent use of an Error Correction Code (ECC) can utilizethe quality indications to detect and reconstruct the data with improvedeffectiveness. Alternatively, a statistics of data quality can beconstructed and digital data values can be associated in a modifiedmanner to prevent data corruption.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a method for operating amemory, including:

storing data, which is encoded with an Error Correction Code (ECC), inanalog memory cells of the memory by writing respective analog inputvalues selected from a set of nominal values to the analog memory cells;

reading the stored data by performing multiple read operations thatcompare analog output values of the analog memory cells to different,respective read thresholds so as to produce multiple comparison resultsfor each of the analog memory cells, wherein at least two of the readthresholds are positioned between a pair of the nominal values that areadjacent to one another in the set of the nominal values;

computing soft metrics responsively to the multiple comparison results;and

decoding the ECC using the soft metrics, so as to extract the datastored in the analog memory cells.

In some embodiments, each of the analog memory cells stores one or morebits of the data, and each of the soft metrics corresponds to one of thebits. In an embodiment, each of at least some of the analog memory cellsstores two or more bits of the data, reading the data includes, for eachof the at least some of the analog memory cells, reading the two or moredata bits in respective two or more decoding stages, and computing thesoft metrics includes modifying a soft metric of a first bit read in afirst decoding stage responsively to a value of a second bit read in asecond decoding stage that precedes the first decoding stage. Modifyingthe soft metric may include conditionally inverting the soft metric ofthe first bit depending on the value of the second bit.

In another embodiment, the method includes making an initial attempt todecode the ECC using an initial set of the read thresholds, such that nomore than one of the read thresholds in the initial set is positionedbetween each pair of the nominal values that are adjacent to oneanother, and comparing the analog output values to the multiple readthresholds upon a failure of the initial attempt.

In yet another embodiment, each comparison result has one of first andsecond possible values, and computing the soft metrics includesdetermining respective first and second counts of the comparison resultshaving the first and second possible values, and computing the softmetrics based on the first and second counts.

In still another embodiment, the method further includes, upon failingto decode the ECC, adding one or more additional read thresholds to themultiple read thresholds, re-computing the soft metrics responsively tothe additional read thresholds, and decoding the ECC using there-computed soft metrics. Adding the additional threshold may includeprogressively increasing a number of the read thresholds until apredetermined condition is met.

In a disclosed embodiment, reading the data from a first group of theanalog memory cells further includes estimating interference caused tothe first group by a second group of the analog memory cells andcanceling the estimated interference. Canceling the estimatedinterference may include modifying the soft metrics associated with thefirst group responsively to the estimated interference. In someembodiment, the method includes, upon failing to decode the ECC in thefirst group, selecting whether to perform one of:

re-reading the data in the second group, so as to re-estimate and cancelthe interference;

re-estimating the interference by reading the data in a third group ofthe memory cells; and

adding one or more additional read thresholds and re-reading the data inthe first group using the additional read thresholds.

In an embodiment, computing the soft metrics includes normalizing thesoft metrics so as not to depend on a number of the read thresholds.Performing the multiple read operations may include positioning themultiple read thresholds at non-uniform intervals with respect to oneanother.

There is additionally provided, in accordance with an embodiment of thepresent invention, a data storage apparatus, including:

an interface, which is operative to communicate with a memory thatincludes a plurality of analog memory cells; and

a memory signal processor (MSP), which is connected to the interface andis coupled to store data, which is encoded with an Error Correction Code(ECC), in the analog memory cells by writing respective input analogvalues selected from a set of nominal values to the analog memory cells,to read the stored data by performing multiple read operations thatcompare analog output values of the analog memory cells to different,respective read thresholds so as to produce multiple comparison resultsfor each of the analog memory cells, wherein at least two of the readthresholds are positioned between a pair of the nominal values that areadjacent to one another in the set of the nominal values, to computesoft metrics responsively to the multiple comparison results, and todecode the ECC using the soft metrics, so as to extract the data storedin the analog memory cells.

There is also provided, in accordance with an embodiment of the presentinvention, a data storage apparatus, including:

a memory device, including:

a plurality of analog memory cells, which are configured to store data,which is encoded with an Error Correction Code (ECC) and written to theanalog memory cells as respective analog input values selected from aset of nominal values; and

reading circuitry, which is coupled to read the stored data byperforming multiple read operations that compare output analog values ofthe analog memory cells to different, respective read thresholds so asto produce multiple comparison results for each of the analog memorycells, wherein at least two of the read thresholds are positionedbetween a pair of the nominal values that are adjacent to one another inthe set of the nominal values, to compute soft metrics responsively tothe multiple comparison results, and to output the computed softmetrics; and

a Memory Signal Processor (MSP) device, which is connected to the memorydevice and is coupled to accept the soft metrics computed by the readingcircuitry, and to decode the ECC using the soft metrics.

There is further provided, in accordance with an embodiment of thepresent invention, a method for operating a memory, including:

storing data, which is encoded with an Error Correction Code (ECC), inanalog memory cells of the memory by writing respective analog inputvalues to the analog memory cells;

reading the stored data by comparing analog output values of the analogmemory cells to a set of read thresholds, so as to produce multiplecomparison results for each of the analog memory cells;

computing soft metrics responsively to the multiple comparison results;

decoding the ECC using the soft metrics, so as to extract the datastored in the analog memory cells; and

upon a failure to successfully extract the data, extending the set ofthe read thresholds by adding one or more new read thresholds to theset, updating the multiple comparison results based on the extended setof the read thresholds, re-computing the soft metrics and re-decodingthe ECC, so as to extract the data.

In an embodiment, extending the set of the read thresholds includesselecting the one or more new read thresholds responsively to the outputanalog values of the analog memory cells. Selecting the one or more newread thresholds may include determining at least one property selectedfrom a group of properties consisting of a number of the new readthresholds and values of the new read thresholds.

The present invention will be more fully understood from the followingdetailed description of the embodiments thereof, taken together with thedrawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram that schematically illustrates a system formemory signal processing, in accordance with an embodiment of thepresent invention;

FIG. 2 is a diagram that schematically illustrates a memory cell array,in accordance with an embodiment of the present invention;

FIG. 3 is a diagram that schematically illustrates read thresholds in aSingle-Level Cell (SLC), in accordance with an embodiment of the presentinvention;

FIG. 4 is a diagram that schematically illustrates read thresholds in aMulti-Level Cell (MLC), in accordance with an embodiment of the presentinvention;

FIG. 5 is a flow chart that schematically illustrates a method forreading data from analog memory cells, in accordance with an embodimentof the present invention;

FIG. 6 is a flow chart that schematically illustrates a method forcomputing soft metrics, in accordance with an embodiment of the presentinvention;

FIG. 7 is a block diagram that schematically illustrates a circuit forcomputing soft metrics, in accordance with an embodiment of the presentinvention;

FIG. 8 is a flow chart that schematically illustrates a method forreading data from analog memory cells, in accordance with anotherembodiment of the present invention;

FIG. 9 is a diagram that schematically illustrates a process for readingdata from analog memory cells, in accordance with yet another embodimentof the present invention;

FIG. 10 is a flow chart that schematically illustrates a method forreading data from analog memory cells, in accordance with still anotherembodiment of the present invention; and

FIG. 11 is a block diagram that schematically illustrates a system formemory signal processing, in accordance with an alternative embodimentof the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS Overview

Embodiments of the present invention provide improved methods andsystems for reading data from analog memory cells, such as Flash memorycells. In some embodiments that are described hereinbelow, a MemorySignal Processor (MSP) stores data, which is encoded with an ErrorCorrection Code (ECC), in an array of analog memory cells. The MSPstores the encoded data by writing respective analog values to theanalog memory cells. The analog values are selected from a set ofnominal analog values, which represent the data.

The MSP reads the data from the analog memory cells by performingmultiple read operations, which compare the analog values written to thecells to multiple read thresholds. The read thresholds are set so thatat least two of them are positioned between a pair of adjacent nominalanalog values. The multiple threshold comparisons produce multiplecomparison results for each of the analog memory cells. The MSP computessoft metrics based on the multiple comparison results. The soft metricsprovide quantitative measures of the levels of confidence or certaintythat are associated with the values read from the memory cells, or ofindividual bits within the memory cells. The MSP decodes the ECC usingthe soft metrics. In some embodiments, the MSP increases the number ofread thresholds in an iterative manner, until successful decoding isachieved.

Some known reading methods differentiate between adjacent memory statesusing a single threshold at any given time. Unlike these known methods,the methods and systems described herein perform multiple readoperations using multiple thresholds, which are positioned betweenadjacent memory states. Typically, multiple thresholds are positioned inboundary regions between adjacent nominal values, so that the multiplecomparison results convey valuable information regarding the statisticaldistribution of the analog values in these regions. As a result, thesoft metrics, which are based on this information, enable the ECCdecoding process to correct a higher number of read errors and toprovide an improved overall error probability.

Some known reading methods modify the threshold values in order toimprove decoding performance. Unlike these known methods, the methodsand systems described herein do not adapt the threshold values, butrather add new thresholds to the existing set, and improve the decodingperformance by refining the accuracy of the soft metrics.

The improved decoding performance achieved by the disclosed methods andsystems enables improving the data storage reliability, storage densityand retention time of memory devices, and enables lowering the memorydevice cost and complexity for a given performance level.

System Description

FIG. 1 is a block diagram that schematically illustrates a system 20 formemory signal processing, in accordance with an embodiment of thepresent invention. System 20 can be used in various host systems anddevices, such as in computing devices, cellular phones or othercommunication terminals, removable memory modules (“disk-on-key”devices), digital cameras, music and other media players and/or anyother system or device in which data is stored and retrieved.

System 20 comprises a memory device 24, which stores data in a memorycell array 28. The memory array comprises multiple analog memory cells32. In the context of the present patent application and in the claims,the term “analog memory cell” is used to describe any memory cell thatholds a continuous, analog value of a physical parameter, such as anelectrical voltage or charge. Array 28 may comprise analog memory cellsof any kind, such as, for example, NAND, NOR and CTF Flash cells, PCM,NROM, FRAM, MRAM and DRAM cells. The charge levels stored in the cellsand/or the analog voltages or currents written into and read out of thecells are referred to herein collectively as analog values.

System 20 stores data in the analog memory cells by programming thecells to assume respective memory states. The memory states are selectedfrom a finite set of possible states, and each state corresponds to acertain nominal analog value. For example, a 2 bit/cell MLC can beprogrammed to assume one of four possible memory states by writing oneof four possible nominal analog values into the cell.

Data for storage in memory device 24 is provided to the device andcached in data buffers 36. The data is then converted to analog voltagesand written into memory cells 32 using a reading/writing (R/W) unit 40,whose functionality is described in greater detail below. When readingdata out of array 28, R/W unit 40 converts the electrical charge, andthus the analog voltages of memory cells 32, into digital samples havinga resolution of one or more bits. The samples are cached in buffers 36.The operation and timing of memory device 24 is managed by control logic48.

The storage and retrieval of data in and out of memory device 24 isperformed by a Memory Signal Processor (MSP) 52. MSP 52 comprises asignal processing unit 60, which processes the data that is written intoand read from device 24. Unit 60 encodes the data to be written into thememory cells using an Error Correction Code (ECC), and decodes the ECCof the retrieved data.

In particular, MSP 52 reads data out of memory cells 32 by comparing thevalues read from the cells to multiple read thresholds. The ECC decodingscheme used by unit 60 operates on soft metrics, which are computedbased on the multiple threshold comparisons. Exemplary methods forreading data and for computing soft metrics are described in detailbelow.

Many known ECC decoding schemes can accept soft metrics of the encodedbits or symbols as input. For example, unit 60 may use a block code suchas the Bose-Chaudhuri-Hocquenghem (BCH) code, Low-Density Parity Check(LDPC) code or Reed-Solomon (RS) code, a trellis code, a turbo-code, orany other suitable ECC and decoding scheme, which is able to operate onsoft metrics. The methods and systems described herein are not limitedto block codes and can be used with convolutional codes, as well.

MSP 52 comprises a data buffer 72, which is used by unit 60 for storingdata and for interfacing with memory device 24. MSP 52 also comprises anInput/Output (I/O) buffer 56, which forms an interface between the MSPand the host system. A controller 76 manages the operation and timing ofMSP 52. Signal processing unit 60 and controller 76 may be implementedin hardware. Alternatively, unit 60 and/or controller 76 may comprisemicroprocessors that run suitable software, or a combination of hardwareand software elements.

The configuration of FIG. 1 is an exemplary system configuration, whichis shown purely for the sake of conceptual clarity. Any other suitableconfiguration can also be used. Elements that are not necessary forunderstanding the principles of the present invention, such as variousinterfaces, addressing circuits, timing and sequencing circuits anddebugging circuits, have been omitted from the figure for clarity.

In the exemplary system configuration shown in FIG. 1, memory device 24and MSP 52 are implemented as two separate Integrated Circuits (ICs). Inalternative embodiments, however, the memory device and MSP may beintegrated on separate semiconductor dies in a single Multi-Chip Package(MCP) or System on Chip (SoC). Further alternatively, some or all of theMSP circuitry may reside on the same die on which memory array 28 isdisposed. An exemplary configuration of this sort is described in FIG.11 below. Further alternatively, some or all of the functionality of MSP52 can be implemented in software and carried out by a processor orother element of the host system. In some implementations, a single MSP52 may be connected to multiple memory devices 24. Additionalarchitectural aspects of certain embodiments of system 20 are describedin greater detail in U.S. Provisional Patent Application 60/867,399,cited above.

In a typical writing operation, data to be written into memory device 24is accepted from the host and cached in I/O buffer 56. The data istransferred, via data buffers 72, to memory device 24. The data may bepre-processed by MSP 52 before it is transferred to the memory devicefor programming. For example, unit 60 may encode the data using an ECC,add certain data for internal use, and/or scramble the data. In device24 the data is temporarily stored in buffers 36. R/W unit 40 convertsthe data to nominal analog values and writes the nominal values into theappropriate cells 32 of array 28.

In a typical reading operation, R/W unit 40 reads analog values out ofthe appropriate memory cells 32 and converts them to soft digitalsamples. The samples are cached in buffers 36 and transferred to buffers72 of MSP 52. In some embodiments, unit 60 of MSP 52 converts thesamples to data bits. As noted above, the range of possible analogvalues is divided into two or more regions, with each regionrepresenting a certain combination of one or more data bits.

As will be described in greater detail further below, the memory cellsare read by comparing their analog values to multiple sets of readthresholds. For each cell, the MSP computes a soft metric based on themultiple comparison results. The soft metrics are then used by the MSPwhen decoding the ECC. The decoded data is transferred via I/O buffer 56to the host system.

Memory Array Structure

FIG. 2 is a diagram that schematically illustrates memory cell array 28,in accordance with an embodiment of the present invention. Although FIG.2 refers to Flash memory cells that are connected in a particular arrayconfiguration, the principles of the present invention are applicable toother types of memory cells and other array configurations, as well.Some exemplary cell types and array configurations are described in thereferences cited in the Background section above.

Memory cells 32 of array 28 are arranged in a grid having multiple rowsand columns. Each cell 32 comprises a floating gate Metal-OxideSemiconductor (MOS) transistor. A certain amount of electrical charge(electrons or holes) can be stored in a particular cell by applyingappropriate voltage levels to the transistor gate, source and drain. Thevalue stored in the cell can be read by measuring the threshold voltageof the cell, which is defined as the minimal voltage that needs to beapplied to the gate of the transistor in order to cause the transistorto conduct. The read threshold voltage is indicative of the chargestored in the cell.

In the exemplary configuration of FIG. 2, the gates of the transistorsin each row are connected by word lines 80. The sources of thetransistors in each column are connected by bit lines 84. In someembodiments, such as in some NOR cell devices, the sources are connectedto the bit lines directly. In alternative embodiments, such as in someNAND cell devices, the bit lines are connected to strings offloating-gate cells.

Typically, R/W unit 40 reads the threshold voltage of a particular cell32 by applying varying voltage levels to its gate (i.e., to the wordline to which the cell is connected) and checking whether the draincurrent of the cell exceeds a certain threshold (i.e., whether thetransistor conducts). Unit 40 usually applies a sequence of differentvoltage values to the word line to which the cell is connected, anddetermines the lowest gate voltage value for which the drain currentexceeds the threshold. Typically, unit 40 reads a group of cells,referred to as a page, simultaneously. Alternatively, R/W unit may useany other technique or circuitry for reading and writing values to andfrom memory cells 32 of array 28.

The memory cell array is typically divided into multiple pages, i.e.,groups of memory cells that are programmed and read simultaneously. Insome embodiments, each page comprises an entire row of the array. Inalternative embodiments, each row (word line) can be divided into two ormore pages. For example, in some SLC devices each row is divided intotwo pages, one comprising the odd-order cells and the other comprisingthe even-order cells. Typically but not necessarily, a two-bit-per-cellmemory device usually has four pages per row, a three-bit-per-cellmemory device has six pages per row, and a four-bit-per-cell memorydevice has eight pages per row.

Erasing of cells is usually carried out in blocks that contain multiplepages. Typical memory devices may comprise several thousand erasureblocks. In a typical two-bit-per-cell MLC device, each erasure block ison the order of 32 word lines, each comprising several thousand cells.Each word line is often partitioned into four pages (odd/even ordercells, least/most significant bit of the cells). Alternatively, otherblock sizes and configurations can also be used. Three-bit-per celldevices often have 192 pages per erasure block, and four-bit-per-celldevices often have 256 pages per block.

Some memory devices comprise two or more separate memory cell arrays,often referred to as planes. Since each plane has a certain “busy”period between successive write operations, data can be writtenalternately to the different planes in order to increase programmingspeed.

Memory Cell Distortion Mechanisms

The analog values (e.g., threshold voltages) stored in memory cells 32may contain various types of distortion, which are caused by differentdistortion mechanisms in array 28. For example, electricalcross-coupling between nearby cells in the array may modify thethreshold voltage of a particular cell. As another example, electricalcharge may leak from the cells over time. As a result of this agingeffect, the threshold voltage of the cells may drift over time from theinitially-written value. Another type of distortion, commonly referredto as disturb noise, is caused by memory access operations (e.g., read,write or erase operations) on certain cells in the array, which causeunintended charge variations in other cells. As yet another example, thesource-drain current of a particular cell can be affected by the chargein adjacent cells, e.g., other cells in the same NAND cell string, viaan effect referred to as Back Pattern Dependency (BPD).

The distortion in memory cells 32 degrades the performance of the memorydevice, e.g., the error probability when reconstructing the data, theachievable storage capacity and/or the achievable data retention period.Performance degradation is particularly severe in MLC devices, in whichthe differences between the different voltage levels that represent thedata are relatively small.

Reading Memory Cells Using Multiple Thresholds

Embodiments of the present invention provide improved methods andsystems for reading data from analog memory cells 32 of array 28, byusing multiple read thresholds. The methods described herein aresuitable for both SLC devices (as illustrated, for example, in FIG. 3below) and MLC devices (as illustrated, for example, in FIG. 4 below).

FIG. 3 is a diagram that schematically illustrates read thresholds in anSLC device, in accordance with an embodiment of the present invention.The figure shows two statistical distributions of the threshold voltagesin a group (e.g., page) of analog memory cells. For a specific page, thediagram represents a histogram of the threshold voltages stored in thememory cells of the page. In the example of FIG. 3, each memory cell isprogrammed to one of two possible nominal levels, i.e., each cell storesa single data bit. Due to various distortion variations among the cellsand various impairment mechanisms, the actual threshold voltages readfrom the memory cells may statistically vary from the nominal levels. Inthe present example, a curve 90A shows the distribution of thresholdvoltages of the cells, which are programmed to store a “1” value. Acurve 90B shows the distribution of threshold voltages of the cells thatare programmed to store “0”.

As can be seen in the figure, curves 90A and 90B overlap. In otherwords, there is a finite probability that a memory cell, which wasprogrammed to a certain bit value, will be erroneously interpreted asbeing programmed to another bit value. The position of the readthreshold or thresholds used to differentiate between “1” and “0” has aconsiderable effect on the probability of error. In some embodiments ofthe present invention, MSP 52 reconstructs the data stored in the memorycells by combining information, which is obtained using multiple readthresholds, in order to reduce the probability of error.

FIG. 3 shows five thresholds denoted T1 . . . T5. In some embodiments,MSP 52 reads each memory cell using each of the thresholds. Each readoperation produces a comparison result, i.e., an indication of whetherthe read threshold voltage is greater or smaller than the threshold usedin the operation. In the exemplary embodiment of FIG. 3, the MSP readseach memory cell five times, using thresholds T1 . . . T5, to producefive respective comparison results. The MSP may go through the differentthresholds at any suitable order. For example, the MSP may begin withthe threshold positioned in the middle of the desired region andgradually move away from this point by adding thresholds on either sideof the initial threshold. Exemplary iterative methods that graduallyincrease the number of thresholds are described further below.

For each memory cell being read, the MSP computes a soft metric usingthe multiple comparison results. The soft metric indicates a confidencelevel or measure of certainty associated with the value read from thememory cell. In some embodiments, the soft metric indicates a likelihoodthat the read value corresponds to a certain data value (e.g., a verylow metric value may indicate a high certainty that the read valuecorresponds to a “1”, a very high metric value indicates that the readvalue is likely to represent a “0”, and intermediate metric valuesindicate lower confidence). In other embodiments, the metric valueindicates the reliability of the read value without indicating aparticular bit value (e.g., low metric value indicates low confidence,high metric value represents high confidence).

In the context of the present patent application and in the claims, theterm “soft metric” refers to any type of quantitative measure thatconveys more than a single bit of information, i.e., more than twopossible values. For example, the soft metric may comprise a fixed- orfloating-point numerical value represented using two or more bits.Another exemplary type of soft metric, sometimes referred to as“erasure,” assigns each read memory cell one of three possiblevalues—“0”, “1” or “uncertain.” Further alternatively, any othersuitable type of soft metric can be used.

Note that when each cell stores multiple data bits, a soft metric valuemay be computed and assigned to each individual bit. For example, in afour-level MLC, one metric value is computed for the Least SignificantBit (LSB) and another metric value is computed for the Most SignificantBit (MSB). Detailed examples of metric computation methods for both SLCand MLC applications are described further below.

MSP 52 may use any suitable method for computing the soft metric valuebased on the multiple comparison results. In some embodiments, the MSPmay use a table, which provides the metric values associated withdifferent combinations of the comparison results. For example, thefollowing table can be used with the five-threshold configuration ofFIG. 3:

Comparison results Metric T1 T2 T3 T4 T5 value 0 0 0 0 0 M1 0 0 0 0 1 M20 0 0 1 0 M3 0 0 0 1 1 M4 . . . . . . . . . . . . . . . . . . 1 1 1 1 0M31 1 1 1 1 1 M32

The table above provides thirty-two soft metric values denoted M1 . . .M32, which correspond to the thirty-two possible combinations of fivecomparison results of thresholds T1 . . . T5. Following the notation ofFIG. 3, a “0” comparison result means that the read value was higherthan the threshold used, and a “1” comparison result means the readvalue was lower than the threshold.

Typically, M1 and M32 will indicate high confidence levels, since thesemetric values correspond to situations in which the read operations withall five thresholds produce the same comparison results. Othercombinations of comparison results will usually be assigned metrics thatindicate lower confidence levels.

Some sets of comparison results may be regarded as inconsistent orself-contradictory. For example, assume T1<T2<T3<T4<T5, and that thefive comparison results produced by thresholds T1 . . . T5 are denotedC1 . . . C5, respectively. The result set ‘1,1,1,0,1’ for a certainmemory cell is inconsistent because it indicates that the analog valueis larger than T4 and smaller than T3, even though T4>T3. Such a resultset may be caused, for example, when the cell has a high level of readnoise in at least one of the read operations. Result sets such as‘1,1,1,1,0’, ‘1,1,1,0,0’, or ‘1,0,0,0,0’, on the other hand, areconsistent.

The MSP may treat inconsistent sets of comparison results in differentmanners, by assigning them different soft metric values. For example,the MSP may regard inconsistent result sets as uncertain and mark themas erasures to the ECC decoding process. Alternatively, the MSP maydisregard or otherwise attempt to resolve some inconsistencies. Forexample, the MSP may regard a ‘1,1,0,1,1,’ result set similarly to a‘1,1,1,1,1’ set, assuming that the “0” comparison result of T3 wascaused by read noise.

Alternatively to using tables, MSP 52 may evaluate a function thatoperates on the multiple comparison results and produces thecorresponding soft metric value. For example, the MSP may evaluate LogLikelihood Ratios (LLRs) of individual bits in each memory cell, whichare defined as

$\begin{matrix}{{{LLR} \equiv {\Lambda( X_{i} )}} = {\log\mspace{14mu}\lbrack \frac{p( {X_{i} =  1 \middle| r } )}{p( {X_{i} =  0 \middle| r } )} \rbrack}} & \lbrack 1\rbrack\end{matrix}$

wherein X_(i) denotes a particular data bit stored in the memory cell inquestion, and r denotes the analog value read from the cell. The use ofLLRs as metrics that are provided to an ECC decoding process isdescribed, for example, in PCT Patent Application PCT/IL2007/000580,entitled “Combined Distortion Estimation and Error Correction Coding ForMemory Devices,” filed May 10, 2007, whose disclosure is incorporatedherein by reference.

In order to calculate the LLR, the MSP may maintain two values for eachmemory cell: (1) the largest read threshold that was found to be belowthe analog value of the cell, denoted V_(a), and (2) the smallest readthreshold that was found to be above the analog value of the cell,denoted V_(b). The LLR of the cell can be shown to be approximated by

$\begin{matrix}{{\Lambda( X_{i} )} \approx {{\log\mspace{14mu}\lbrack {{Q\{ \frac{V_{a} - T_{1}}{\sigma} \}} - {Q\{ \frac{V_{b} - T_{1}}{\sigma} \}}} \rbrack} - {\log\mspace{11mu}\lbrack {{Q\{ \frac{V_{a} - T_{0}}{\sigma} \}} - {Q\{ \frac{V_{b} - T_{0}}{\sigma} \}}} \rbrack}}} & \lbrack 2\rbrack\end{matrix}$wherein T1 denotes the center analog value of the nearest distributionthat has “1” as its data bit, and T0 denotes the center value of thenearest distribution having “0” as its data bit. The distribution of ris assumed Gaussian with variance σ².

As the memory cell is read with an increasing number of read thresholds,the MSP updates V_(a) and V_(b). At each stage, the actual analog valueof the cell is known to be within the interval [V_(a), V_(b)]. As thenumber of thresholds increases, the interval shrinks, the uncertaintybecomes smaller and the estimated LLR becomes more accurate.

Further alternatively, the MSP may use any other suitable method ormechanism for computing the soft metric values based on the multiplecomparison results.

MSP 52 uses the soft metrics when decoding the ECC. In a typicalapplication, the data stored in a group of memory cells, such as in acertain memory page, forms a single codeword. When decoding a certainECC codeword, signal processing unit 60 of the MSP uses the soft metricvalues of the memory cells in the group. As a result, memory cells thatare considered to have a high confidence level are given more weight inthe ECC decoding process, and vice versa.

FIG. 4 is a diagram that schematically illustrates read thresholds in anMLC device, in accordance with an embodiment of the present invention.In the example of FIG. 4, each memory cell is programmed to one of fourpossible nominal levels, thus storing two bits of data. Curves 94A . . .94D show the threshold voltage distributions of the memory cells thatare programmed to store “11”, “01”, “00” and “10” data, respectively. Inthe present example, MSP 52 reads the memory cells using five sets ofthresholds. Each threshold set comprises three thresholds, which aretypically positioned in the three boundary regions between pairs ofadjacent distribution curves. The threshold sets are listed in thefollowing table:

Threshold set Thresholds 1 T11, T21, T31 2 T12, T22, T32 3 T13, T23, T334 T14, T24, T34 5 T15, T25, T35

In some embodiments, MSP 52 reads the threshold voltage of the cellusing each of the fifteen thresholds, and computes a soft metric basedon the fifteen comparison results. The MSP may use any type of softmetric and any method of computing the metric value based on themultiple comparison results. The MSP uses the soft metric values asinput to the ECC decoding process, as explained above.

In alternative embodiments, the memory cell is read in two stages,corresponding to the two bits stored in the cell. For example, in theconfiguration of FIG. 4, the R/W unit performs a first set ofcomparisons using the five thresholds T21, T22, T23, T24 and T25, i.e.,the thresholds located in the middle of the voltage axis, between curves94B and 94C. The MSP computes a first soft metric based on the fivecomparison results obtained using these five thresholds. Note that bothnominal levels located above thresholds T21 . . . T25 have an LSB valueof “0” and that both nominal levels located below thresholds T21 . . .T25 have an LSB value of “1”. Therefore, the first soft metriccorresponds to the LSB. Once the LSB is decoded, the R/W unit performs asecond set of comparisons. The R/W unit may use thresholds T11 . . . T15or thresholds T31 . . . T35 in the second stage, depending on thedecoded value of the LSB. If the LSB was determined to be “1”, i.e., theread value was determined to be in the lower part of the voltage range,the MSB will be decoded using thresholds T11 . . . T15 in the secondstage. If the LSB was decoded as “0”, the MSB will be decoded usingthresholds T31 . . . T35. The MSP computes a second metric, whichcorresponds to the MSB, based on the five comparison results obtained inthe second comparison stage.

A similar multi-stage comparison process can be carried out inmulti-level cells storing a higher number of bits. For example, ineight-level (3 bit/cell) cells, the MSP and R/W unit may perform athree-stage comparison process to decode the individual bits. Apart fromthe first stage, the selection of the thresholds used in each stagetypically depends on the decoded values of the previous bits.

In alternative multi-stage reading processes, each bit is readindependently of the other bits. For example, referring to FIG. 4, theLSB can be read using thresholds T21 . . . T25. The MSB is read bysequentially reading the cell using both thresholds T11 . . . T15 andT31 . . . T35. If the comparison results indicate that the analog valueis between T11 . . . T15 and T31 . . . T35, the bit is determined to be“0”. If, on the other hand, the comparison results indicate that theanalog value is larger than T31 . . . T35 or smaller than T11 . . . T15,the bit is determined to be “1”. In this example, the comparison resultsto thresholds T21 . . . T25, which were used for reading the LSB, arenot used for reading the MSB. Similar processes may be performed forother types of MLC, such as eight-level cells storing three bits percell.

The threshold configurations shown in FIGS. 3 and 4 above are exemplaryconfigurations, which were chosen purely for the sake of conceptualclarity. In alternative embodiments, system 20 may use any desirednumber of nominal levels, any other mapping of bit values to nominallevels and any desired number of threshold sets. Although FIGS. 3 and 4show thresholds that are spaced at regular increments, the methods andsystems described herein may use irregularly-spaced thresholds, as well.In MLC devices, the threshold spacing may vary from one voltage regionto another. For example, in FIG. 4, thresholds T11 . . . T15 may bespaced differently than thresholds T21 . . . T25. Different thresholdspacing may be used, for example, when different analog valuedistributions have different shapes or different spacing with respect toone another. The MSP may modify the threshold spacing, or otherwiseselect the threshold values to use, such as based on estimation of theanalog value distributions.

FIG. 5 is a flow chart that schematically illustrates a method forreading data from analog memory cells 32, in accordance with anembodiment of the present invention. For a certain memory cell, themethod begins with system 20 performing multiple read operations usingrespective multiple thresholds, at a reading step 100. The multiple readoperations produce respective multiple comparison results, i.e.,indications of whether the threshold voltage of the cell is smaller orgreater than the different thresholds. MSP 52 computes a soft metric ofthe memory cell based on the multiple comparison results, at a metriccomputation step 104.

The MSP typically repeats the process of steps 100 and 104 above over agroup of memory cells, whose data forms a single ECC codeword. In atypical implementation, R/W unit 40 reads the cells of an entire page ofthe memory device, using a particular threshold value, simultaneously.Once the soft metrics of the cells that store a certain codeword arecomputed, the MSP decodes the codeword using the metrics, at a decodingstep 108. The MSP extracts the decoded data, at a data extraction step112. The decoded data is typically output to the host system.

The multiple-threshold reading methods described herein can also beviewed as an efficient means for obtaining accurate informationregarding the stored analog values using a relatively small number ofread operations. Theoretically, if the exact analog values stored in thememory cells were known to the MSP (e.g., by employing high-resolutionanalog-to-digital conversion), this information could be used to extractprobability measures on the stored data. However, the basic readoperation of analog memory devices, such as Flash memories, usuallycomprises comparison operations, which compare the analog value storedin a cell to a single threshold. In order to obtain the analog valuewith a given resolution, the entire possible voltage range would have tobe searched or scanned with the desired resolution. For example, if therange of possible analog values is 0-4V, and the desired resolution is10 mV, 400 read operations would be needed. In practice, however, muchof the valuable statistical information can be obtained by performing amuch smaller number of read operations, for example by positioning theread thresholds in a region around the midpoint between distributions.The methods and systems described herein thus provide efficient means ofgaining insight to such analog value statistics using a relatively smallnumber of read operations.

In many practical cases, performing a large number of read operations ona certain memory cell is a computationally-intensive task, whichcomplicates and slows down the data retrieval process. Moreover, the ECCis usually strong enough to successfully decode the vast majority ofcodewords, even when the memory cells are read using a single set ofthresholds. Therefore, in some embodiments, the MSP initially reads thememory cells using a single set of thresholds. The MSP reverts to readthe memory cells that correspond to a certain codeword using themultiple-threshold methods described herein only when the ECC decodingprocess fails.

The methods of FIGS. 3-5 above can be applied iteratively, graduallyincreasing the number of thresholds used. For example, the MSP mayattempt to reconstruct the data using soft metrics that are based on twosets of thresholds. If the data cannot be reconstructed (i.e., if theECC fails), the MSP can re-read the memory cells using a third thresholdset. The iterations may continue until ECC decoding succeeds, or untilreaching a predetermined maximum number of threshold sets. Note that ateach stage of the iterative process, the MSP computes the soft metricsbased on the multiple comparison results that are available so far. Insome cases, the MSP may use information, such as metric values, whichwas calculated in previous iterations. The iterative process enables agradual increase in the number of computations, only as needed to carryout successful decoding.

Soft Metrics Based on Counting Computation Results

In some embodiments, the MSP computes the soft metric value based on thenumber of computation results falling on either side of the thresholds.(In the description that follows, a “0” comparison result means the readvalue was higher than the threshold, and vice versa. This convention,however, is chosen purely for the sake of convenience, and the oppositeconvention can also be used.) Consider, for example, the exemplary SLCembodiment of FIG. 3 above. In this embodiment, out of the fivecomparison results, if the number of “0” comparison results isconsiderably higher than the number of “1” results, it is likely thatthe cell was programmed to “0”. Similarly, if the number of “1”comparison results is considerably higher than the number of “0”results, the programmed bit is likely to be “1”. Similar logic can alsobe used within each stage of the multi-stage comparison process thatdecodes the individual bits of a MLC cell, which was described in FIG. 4above.

FIG. 6 is a flow chart that schematically illustrates an exemplarymethod for computing soft metrics, in accordance with an embodiment ofthe present invention. The method description refers to an SLCapplication and makes reference to FIG. 3 above. This choice, however,is made purely for the sake of simplicity of explanation. The method cansimilarly be used in MLC applications, as well.

The method begins with the MSP defining multiple thresholds, at athreshold definition step 116. Typically but not necessarily, thethresholds are defined within the boundary region between the voltagedistribution. In FIG. 3, five thresholds are defined in the region inwhich curves 90A and 90B overlap. For example, assuming the mid-pointbetween curves 90A and 90B is at 1 volt, and that the thresholds can berepresented at a resolution of 20 mV, a set of thresholds can be definedto cover the voltage range of 1V±40 mV at 20 mV intervals.

The MSP reads the memory cells using the multiple thresholds, at areading step 120. The MSP counts the number of comparison resultsfalling on either side of the thresholds, at a counting step 124. Inother words, the MSP determines the number of “0” comparison resultsand/or the number of “1” results out of the total number of thresholdcomparisons.

The MSP computes a soft metric associated with the cell (or with anindividual bit within the cell) based on the count of comparisonresults, at a metric computation step 128. For example, assuming thefive-threshold configuration of FIG. 3 above and a four-bit metricvalue, the MSP may compute the soft metric according to the followingtable:

Number of “0” Number of “1” computation results computation results Softmetric value 0 5  “1111” = 15 1 4  “1100” = 12 2 3 “1001” = 9 3 2 “0110”= 6 4 1 “0011” = 3 5 0 “0000” = 0

In the table above, if all five computation results are “1”, the storeddata bit is “1” with high likelihood, therefore the maximum metric valueof “1111” is assigned. At the other extreme, if all five comparisonresults are “0”, the stored bit is likely to be “0”, and the minimummetric value of “0000” is assigned. If some comparison results are “0”and others are “1”, the metric value is set to an intermediate value,which grows monotonously with the number of “1” results out of thetotal.

Alternatively, any other suitable method for determining the soft metricvalue based on the count of comparison results can be used. The metriccomputation may be implemented by querying a table that holds the metricvalues and is indexed by the count of comparison results, evaluating afunction that operates on the count of the comparison results, or usingany other suitable mechanism.

Exemplary Hardware Implementation for MLC Metric Computation

As noted above, when computing the soft metrics of individual bits in amulti-level cell, the selection of thresholds may depend on the valuesof previously-decoded bits. Moreover, the values of previously-decodedbits may in some cases affect the metric value itself.

Consider, for example, the four-level cell configuration of FIG. 4above. When reading the data out of such a cell in a two-stage process,the LSB is first decoded by determining whether the value read from thecell falls on the left- or right-hand-side of thresholds T21 . . . T25.Note that in the example of FIG. 4, the two nominal levels located belowthese thresholds have an LSB value of “1”, and the two nominal levelslocated above the thresholds have an LSB value of “0”.

The second decoding stage (decoding of the MSB) depends on the resultsof the first stage. When the LSB is “0”, decoding the MSB comprisesdetermining whether the read value is likely to belong to curve 94C orto curve 94D. When the LSB is “1”, decoding the MSB comprisesdetermining whether the read value is likely to belong to curve 94A orto curve 94B.

Note, however, that when comparing curves 94A and 94B (i.e., whenLSB=“1”), high threshold voltages correspond to MSB=“0” and lowthreshold voltages correspond to MSB=“1”. When comparing curves 94C and94D (i.e., when LSB=“0”) the situation is reversed, with high thresholdvoltages corresponding to MSB=“1” MSB and low threshold voltagescorresponding to MSB=“0”. In such a situation, the soft metric valuethat depends on the count of comparison results should sometimes beinverted, so as to maintain the convention that a high metric valuecorresponds to “0” data. The decision whether or not to invert themetric value depends on the value of the previous bit. Equivalently, thevalue of the currently-read bit can be inverted instead of inverting themetric value. The conditional operation of inverting a value only if aprevious value is equal to “1” can be implemented by performing aneXclusive-OR (XOR) operation between the current and previous bitvalues.

FIG. 7 is a block diagram that schematically illustrates an exemplarycircuit for computing soft metrics in a multi-level cell, in accordancewith an embodiment of the present invention. Although the descriptionthat follows refers to a hardware or firmware implementation, a similarmechanism can be implemented in software, or as a combination ofsoftware and hardware elements.

The circuit of FIG. 7 computes soft metrics of the LSBs and MSBs of agroup of four-level cells, assuming the LSBs represent a certain memorypage and the MSBs represent another page. The LSB page is read first andis referred to as the previous page. The MSB page is read second and isreferred to as the current page. The computation process of the metricsof the current page makes conditional inversion (XOR) operationsdepending on the bit values of the previous page.

The circuit comprises a XOR circuit 134, which performs a bit-wise XORoperation between a byte 130 of hard bit decisions from the current page(MSBs) and a byte 132 of previously-decoded data bits (LSBs) from theprevious page. Thus, for a particular cell, when the previously-decodedLSB is “1”, the currently-read MSB is inverted. An adder 136 sums theresults of the XOR operations. The adder output is accumulated as a softmetric 140 of the MSB. A vector 138 holds the accumulated metrics of theMSBs of the different cells. The same circuit can also be used tocompute the soft metrics of the LSBs, which do not depend on anyprevious values. In order to compute the LSB soft metrics, byte 132 isfilled with zeros so that the XOR operation is bypassed and byte 130 isprovided to adder 136 unchanged.

The circuit of FIG. 7 refers to four-level, 2 bit/cell MLC. Similarcircuits can be used, however, to compute soft metrics for other typesof multi-level cells, such as eight-level, 3 bits/cell MLC.

In alternative embodiments, the soft metrics of individual bits of amulti-level cell can be calculated independently for different bits.These methods may be of particular benefit when the read data values ofprevious bits are not available when reading a certain bit. Referring tothe 2 bit/cell example of FIG. 4 above, the soft metrics of the MSB maybe computed without knowledge of the LSB. As noted above, the MSB valuecan be assumed to be “0” if the analog value falls between thresholdsT11 . . . T15 and T31 . . . T35, and “1” otherwise. In order to computea soft metric for such a reading process, the MSP may group thethresholds in pairs that move progressively inwards into the region inwhich MSB=“0”. The MSP counts the comparison results falling insideand/or outside the MSR=“0” interval using the different threshold pairs.

In the present example, the MSP forms the pairs (T14, T35), (T12, T33),(T11, T31), (T13, T32) and (T15, T34). For each pair, the MSP performstwo read operations and checks whether the read value falls in theinterval between the thresholds, or outside the interval. The MSP countsthe number of threshold pairs in which the analog value falls betweenthe two thresholds (indicating MSB=“0”) and/or the number of thresholdpairs in which the analog value falls outside the interval between thetwo thresholds (indicating MSB=“1”). The MSP computes a soft metricbased on the counts.

A similar method can be applied to eight-level, 3 bit/cell MLC. Assume,for example, an eight-level MLC device whose eight levels are denoted L1. . . L8 and are mapped to the bit triplets ‘111’, ‘011’, ‘001’, ‘101’,‘100’, ‘000’, ‘010’, ‘110’, respectively. The MSP can compute the softmetric of the MSB (leftmost bit in the triplet) of such a cellindependently of the other bits by performing comparisons using foursets of multiple thresholds. Each threshold set is positioned betweenadjacent levels having different MSB values. In the present example, oneset is positioned between levels L1 and L2, another set between L3 andL4, a third set between L5 and L6 and a fourth set between L7 and L8.The four threshold sets divide the analog value axis into five intervalsdenoted I1 . . . I5, such that the MSB has the same value within eachinterval.

Using this division, the MSP determines that the MSB is “0” if the readanalog value read from the cell falls within interval I2 or I4, and “1”if the analog value falls within interval I1, I3 or I5. In order tocompute the soft metric of the MSB, the MSP forms groups of fourthresholds, with each group containing one threshold from each set.Moving from group to group, each threshold is moved in the direction inwhich the MSB value transition is from “1” to “0”. For each thresholdgroup, the MSP performs four read operations and checks whether the readvalue falls in intervals corresponding to “1” or in intervalscorresponding to “0”. The MSP counts the number of threshold groups inwhich the analog value falls in intervals that correspond to MSB=“0”and/or the number of groups in which the analog value falls in intervalsthat correspond to MSB=“1”. The MSP computes a soft metric based on thecounts.

Typically but not necessarily, soft metrics that are based on countingcomparison results of a given type assume that the read thresholds arepositioned symmetrically around the midpoint between distributions.

Gradually Increasing the Number of Thresholds

The comparison and metric computation operations described above consumeboth time and computation resources, which grow with the number ofthresholds. Therefore, it is sometimes advantageous to use only as manythresholds as needed to successfully reconstruct the data. In someembodiments, the MSP initially attempts to compute the soft metrics anddecode the data with a relatively small number of thresholds, andincrease their number only when needed.

For example, the MSP may make an initial attempt to decode the ECC usingan initial set of read thresholds in which only a single threshold ispositioned between each pair of adjacent nominal values (memory states).In these embodiments, the MSP reverts to multiple-threshold decodingupon failure of the initial decoding attempt.

FIG. 8 is a flow chart that schematically illustrates an exemplarymethod for reading data from analog memory cells by gradually increasingthe number of thresholds, in accordance with another embodiment of thepresent invention. Initially, it is assumed that the MSP attempted todecode a particular codeword stored in a group of memory cells usingsoft metrics that were obtained using a certain number of thresholds,and that ECC decoding has failed. The metrics are assumed to be based onthe count of comparison results, as explained above.

The method begins with the MSP adding one or more additional thresholdsto the set of thresholds used, and reading the group of memory cellsusing the added thresholds, at a threshold addition step 142.

The MSP updates the count of comparison results (i.e., the number of “0”and/or “1” results out of the total), at a count updating step 144. Theupdated count reflects the comparison results of the previous thresholdsas well as of the newly-added thresholds. The MSP then computes the softmetrics based on the updated accumulated count of comparison results,and a metric updating step 146.

In some cases, the MSP may compute the metrics from scratch at eachiteration. Alternatively, the MSP may store the metric values and/orcomparison result counts from previous iterations, and update them toaccount for the newly-added comparison results. Generally, the softmetric computed at a given iteration may depend on the currentcomparison result count, on previous counts and on previous metricvalues.

The MSP computes soft metrics based on the accumulated count ofcomparison results, at a metric computation step 146. Any suitablemetric computation method can be used, such as the exemplary methodsdescribed above. The MSP attempts to decode the codeword using the softmetrics, at an ECC decoding step 148. The MSP checks whether the ECCdecoding was successful, at an ECC checking step 150. If successful, theMSP extracts and outputs the data, at a data extraction step 152, andthe method terminates.

If, on the other hand, ECC decoding fails, the method loops back tothreshold addition step 142 above. The MSP adds one or more additionalthresholds to the set of thresholds, computes soft metrics based on theextended set, and attempts to decode the ECC again.

The method of FIG. 8 enables the MSP to use only as many thresholds asneeded to successfully decode the ECC. When distortion is not severe,most codewords can be decoded using a small number of thresholds,enabling a high overall or average reading speed.

Alternatively to continuing the iterations until successful decoding ofthe ECC, the MSP may evaluate any other suitable condition, and stop theiterative process when the condition is met. For example, the MSP maycontinue to add thresholds until reaching a maximum number ofthresholds, or a maximum number of iterations.

In some embodiments, the ECC decoding process may comprise an iterativeprocess. Iterative decoding processes are commonly used to decode codessuch as LDPC and turbo codes. In these embodiments, the iterativedecoding process is provided with increasingly-improving metrics, whichare based on an increasing number of read thresholds. In other words,the iterative decoding process starts decoding using metrics, which arebased on a certain initial number of thresholds. Subsequent iterationsof the iterative decoding process are provided with metrics that arebased on an increasing number of read thresholds, until the iterativedecoding process converges to a valid codeword.

Additionally or alternatively to using an ECC in the method of FIG. 8,the MSP may use an error detection code, such as a Cyclic RedundancyCheck (CRC) or checksum. In such embodiments, the MSP iteratively addsread thresholds until the error detection code detects no errors. Thus,in the context of the present patent application and in the claims, theterm “ECC” is used to address various types of error detection codes, aswell. In some embodiments, the MSP may use an error detection code todetermine when to stop adding new thresholds, even though the data isencoded using an ECC. This scheme may be advantageous, for example, whenthe ECC does not provide a reliable indication of decoding success orfailure.

The MSP may use various methods and criteria for selecting how manythresholds to add at each iteration, and in which order. For example,thresholds can be added two at a time, gradually moving away from theinitial threshold position in both directions. In other words, assumingthe MSP initially attempts to use a threshold denoted T and that thethresholds are spaced at regular intervals of Δ, the threshold sets inthe first four iterations are:

{T, T+Δ, T−Δ}

{T, T+Δ, T−Δ, T+2Δ, T−2Δ}

{T, T+Δ, T−Δ, T+2Δ, T−2Δ, T+3Δ, T−3Δ}

{T, T+A, T−Δ, T+2Δ, T−2Δ, T+3Δ, T−3Δ, T+4Δ, T−4Δ}

Metric Normalization and Interference Cancellation

When computing soft metrics that depend on varying numbers ofthresholds, such as in the method of FIG. 8 above, the possible range ofmetric values may vary with the number of thresholds used. For example,when the soft metric comprises the count of comparison results, themetric values based on three thresholds will be in the range [0 . . .3], whereas metric values based on five thresholds will be in the range[0 . . . 5]. This effect is generally undesirable. In other words, it isgenerally desired to provide the ECC decoder with metrics, which use thesame dynamic range for quantifying confidence or certainty, regardlessof the number of threshold comparisons on which the metric is based.

In some embodiments, the MSP normalizes the soft values read from thememory cells based on the number of thresholds. For example, the MSP mayapply bit extension to the values to reach a certain constant number ofbits, e.g., five-bits. For example, the bit-extended value may be givenby

$\begin{matrix}{\text{ExtendedValue} = \begin{Bmatrix}0 & {{Val} = 0} \\{MaxVal} & {{Val} = N} \\{{Val} + \frac{\text{MaxVal} - N}{2}} & {0 < {Val} < N}\end{Bmatrix}} & \lbrack 3\rbrack\end{matrix}$wherein Val denotes the input soft value and N denotes the number ofthresholds used to evaluate Val. Max Val denotes the maximum value ofthe bit-extended soft value, e.g., 31 for five-bit representation.Alternatively, the MSP may apply any other suitable data scalingmechanism.

In some embodiments, the MSP has information regarding the level ofdistortion or interference in the memory cells being read. Variousmethods can be used to estimate interference levels in memory cells.Exemplary methods are described in PCT Patent ApplicationPCT/IL2007/000580, cited above and in PCT Patent ApplicationPCT/IL2007/000576, entitled “Distortion Estimation and Cancellation inMemory Devices,” filed May 10, 2007, and PCT Patent ApplicationPCT/IL2007/001059, entitled “Estimation of Non-Linear Distortion inMemory Devices,” filed Aug. 27, 2007, whose disclosures are incorporatedherein by reference.

When an estimate of the interference is available to the MSP, the MSPmay add the effect of the interference to the soft values, or otherwisemodify the soft values based on the estimated interference, before thesevalues are provided to the ECC decoder.

FIG. 9 is a diagram that schematically illustrates a process for readingdata from analog memory cells, which involves data scaling andinterference cancellation, in accordance with yet another embodiment ofthe present invention. Although the configuration of FIG. 9 is used todemonstrate both interference cancellation and scaling, each mechanismmay be carried out with or without the other.

In the process of FIG. 9, a scaling module 154 accepts theconditionally-inverted soft values read from the memory cells (e.g., theoutputs of XOR circuit 134 of FIG. 7 above). Module 154 also accepts anindication of the iteration number and/or the number of thresholds thatare currently used. Module 154 applies bit extension or other scaling tothe input soft values. The amount of scaling depends on the inputiteration number.

The scaled soft values are provided to an interference cancellationmodule 156, which also accepts estimates of the interference level inthe respective memory cells. Module 156 subtracts or otherwise cancelsout the interference estimates from the corresponding soft values, toproduce soft values that are properly scaled and contain reduced levelsof interference. The soft values are provided to a metric computationmodule 158, which computes the soft metrics and provides them to the ECCdecoder.

Trading-Off Threshold Comparisons and Interference Estimation

Re-reading cells with additional thresholds and estimating theinterference from neighboring memory cells are two operations that onone hand improve the reading performance, and on the other hand consumetime and computational power. In some embodiments, the MSP may combinethe two operations and trade-off one operation for another. For example,the MSP may determine at each iteration whether it is preferable torefine the decoding accuracy by re-reading the current page using anadditional threshold, or to refine the interference estimation byreading (or re-reading) a group of interfering cells.

FIG. 10 is a flow chart that schematically illustrates a method forreading data from analog memory cells that involves trading-offre-reading and interference estimation, in accordance with anotherembodiment of the present invention.

The method begins with the MSP reading a page of memory cells, at areading step 160. At each cycle of the process, the MSP may select toeither (1) re-read the desired page using an additional threshold, or(2) read a page of interfering cells. The MSP may apply various policiesor heuristics in determining which of the two actions to take at eachcycle. The MSP may read different groups of interfering cells atdifferent cycles.

For example, the MSP may alternate between the two operations, thusadding a threshold every two cycles and estimating interference everytwo cycles. Alternatively, the MSP may choose which action to take basedon the estimated level of the distortion. For example, if recentinterference estimations indicate that the level of interference is low,the MSP may give precedence to adding threshold comparisons, and refinethe interference estimation at larger intervals. Further alternatively,the decision may depend on the type of page being read. For example,even- and odd-order pages may experience different interference levels,and the MSP may apply different decision logic for different page types.Pages located on the last word line in a block may also experiencedifferent interference levels and may be treated differently. Since theinterference may depend on the order in which the pages were written,different trade-offs may apply to higher- and lower-number pages withina word line.

In some cases, memory cells within the desired page may causeinterference to one another. Thus, the group of interfered cells and thegroup of interfering cells may sometimes overlap.

Based on the updated information, the MSP subtracts the interferenceestimation from the read soft values, at an interference cancellationstep 162, and computes the soft metrics, at a metric calculation step164. The MSP then decodes the ECC, at a decoding step 166, and checkswhether ECC decoding was successful, at a success checking step 168.

If the ECC was decoded successfully, the method terminates, at a successtermination step 170, and the MSP typically extracts and outputs thedata. Otherwise, the MSP checks whether the number of iterations(cycles) exceeds a predetermined maximum number, at an iteration numberchecking step 172. If the maximum number of iterations was exceeded, themethod terminates without successfully reading the data, at an errortermination step 174. Otherwise, the method loops back to reading step160 above, and the MSP again determines whether to add another thresholdor refine the interference estimation in the next cycle.

In both iterative methods of FIGS. 8 and 10 above, the MSP may selectthe number of new thresholds that are added at a particular iterationbased on the values read from the cells or the data represented by thesevalues. For example, when the MSP detects severe ECC failure or anexceptionally high level of interference, it may decide to add a highnumber of thresholds. The MSP may also determine the values (i.e.,positions) of the new thresholds based on the read values or read data.For example, the values of new thresholds that are added in response toECC failure may be different from the values of thresholds added inresponse to high interference.

Performing Multiple Read Operations Internally to the Memory Device

When using the methods and systems described above, the multiplecomparison results associated with the multiple thresholds are typicallycommunicated from memory device 24 to MSP 52. The resultingcommunication bandwidth between the memory device and the MSP may becomeprohibitive, especially when using a large number of threshold setsand/or when the number of nominal levels per memory cell is high. Insome practical cases, the communication bandwidth over the interfacebetween the MSP and the memory device may become the limiting factorthat determines the memory access speed of system 20. This effectbecomes even more severe when a single MSP 52 is connected to multiplememory devices 24.

In alternative embodiments of the present invention, some of there-reading functions are carried out internally to the memory device, soas to reduce the communication bandwidth between the memory device andthe MSP.

FIG. 11 is a block diagram that schematically illustrates a system 200for memory signal processing, in accordance with an alternativeembodiment of the present invention. In the exemplary embodiment of FIG.11, multiple memory devices 204 are connected to an MSP 208 over anexternal bus 212. Each memory device 204 comprises a memory cell array216 and a R/W unit 220, which are similar to array 28 and R/W unit 40 ofFIG. 1 above, respectively.

Unlike the embodiment shown in FIG. 1 above, each memory device 204comprises a threshold setting and metric calculation unit 224, alsoreferred to as “metric calculation unit” for brevity. Unit 224 isconnected to R/W unit 220 by an internal bus 228. When the memory deviceaccepts a request to retrieve data from a group of memory cells (e.g., apage), unit 224 controls R/W unit 220 to set the appropriate thresholdvalues and read the memory cells using the thresholds, such as using anyof the methods described above. The R/W unit carries out the multiplecomparison operations and sends the corresponding comparison results tounit 224. Unit 224 computes the soft metrics based on the comparisonresults, and sends the metric values over external bus 212 to MSP 208.

MSP 208 comprises an ECC decoder 232. The ECC decoder accepts the softmetrics sent from unit 224 of memory device 204 and decodes the ECCbased on the metrics. The MSP typically outputs the decoded data to thehost system. When MSP 208 controls multiple memory devices 204, a singleECC decoder may decodes the data sent from all the memory devices.Alternatively, multiple ECC decoders may be used.

When using the configuration of FIG. 11, the communication bandwidthbetween the MSP and the memory device is significantly reduced incomparison with the configuration of FIG. 1 above, since individualcomparison results are not communicated to the MSP. Instead, unit 224sends the soft metric values, typically comprising a single value foreach read memory cell. The large communication bandwidth needed tocommunicate the multiple comparison results is confined to internal bus228, i.e., internally to the memory device. A high bandwidth bus of thissort is considerably simpler to implement internally to the memorydevice than between separate devices. Moreover, the traffic over theinternal bus comprises only the traffic generated by the particularmemory device, regardless of the number of memory devices controlled bythe MSP.

The functional partitioning between R/W unit 220 and metric calculationunit 224 is an exemplary partitioning, which is chosen purely for thesake of conceptual clarity. In alternative embodiments, the reading,threshold comparison, threshold setting and metric computation functionscan be partitioned in any other way, as desired. Thus, R/W unit 220,internal bus 228 and metric calculation unit 224 are collectivelyregarded as a reading circuit, which reads the analog memory cell andproduces soft metrics.

As noted above, the soft metric computation sometimes takes into accountestimation and cancellation of the interference in the read memorycells. In some embodiments, the interference estimation and cancellationfunctionality can also be carried out by the reading circuit internallyto memory device 204, e.g., by unit 224. In these embodiments, unit 224sends to the MSP soft metrics, in which the interference is alreadytaken into account. Some aspects of carrying out signal processingfunctions internally to the memory device are described in U.S.Provisional Patent Application 60/917,653, cited above.

Although the embodiments described herein mainly address retrieving datafrom solid-state memory devices, the principles of the present inventioncan also be used for storing and retrieving data in Hard Disk Drives(HDD) and other data storage media and devices.

It will thus be appreciated that the embodiments described above arecited by way of example, and that the present invention is not limitedto what has been particularly shown and described hereinabove. Rather,the scope of the present invention includes both combinations andsub-combinations of the various features described hereinabove, as wellas variations and modifications thereof which would occur to personsskilled in the art upon reading the foregoing description and which arenot disclosed in the prior art.

The invention claimed is:
 1. A method for operating a memory,comprising: storing data, which is encoded with an Error Correction Code(ECC), in analog memory cells of the memory by writing to the analogmemory cells respective analog input values that program the analogmemory cells to a set of memory states; reading the stored data multipletimes from each analog memory cell by performing multiple readoperations that compare analog output values of the analog memory cellsto different, respective read thresholds so as to produce multiplecomparison results for each of the analog memory cells, wherein theanalog output values associated with each memory state lie in arespective analog value region, wherein analog value regions areseparated by one or more boundary regions, and wherein at least two ofthe read thresholds are positioned in a boundary region between a pairof adjacent ones of the analog value regions; computing soft metricsresponsively to the multiple comparison results; and decoding the ECCusing the soft metrics, so as to extract the data stored in the analogmemory cells; wherein a plurality of the memory cells stores two or morebits of the data, wherein reading the data comprises, for the pluralityof the memory cells, reading the two or more data bits in respective twoor more decoding stages, and wherein computing the soft metricscomprises modifying a soft metric of a first bit read in a firstdecoding stage responsively to a value of a second bit read in a seconddecoding stage that precedes the first decoding stage; and whereinmodifying the soft metric comprises conditionally inverting the softmetric of the first bit depending on the value of the second bit.
 2. Themethod according to claim 1, wherein each of the analog memory cellsstores one or more bits of the data, and wherein each of the softmetrics corresponds to one of the bits.
 3. The method according to claim2, wherein each of at least some of the analog memory cells stores twoor more bits of the data, wherein reading the data comprises, for eachof the at least some of the analog memory cells, reading the two or moredata bits in respective two or more decoding stages, and whereincomputing the soft metrics comprises modifying a soft metric of a firstbit read in a first decoding stage responsively to a value of a secondbit read in a second decoding stage that precedes the first decodingstage.
 4. The method according to claim 3, wherein modifying the softmetric comprises conditionally inverting the soft metric of the firstbit depending on the value of the second bit.
 5. The method according toclaim 1, and comprising making an initial attempt to decode the ECCusing an initial set of the read thresholds, such that no more than oneof the read thresholds in the initial set is positioned in any givenboundary region, and comparing the analog output values to the multipleread thresholds upon a failure of the initial attempt.
 6. The methodaccording to claim 1, wherein each comparison result has one of firstand second possible values, and wherein computing the soft metricscomprises determining respective first and second counts of thecomparison results having the first and second possible values, andcomputing the soft metrics based on the first and second counts.
 7. Themethod according to claim 1, and comprising, upon failing to decode theECC, adding one or more additional read thresholds to the multiple readthresholds, re-computing the soft metrics responsively to the additionalread thresholds, and decoding the ECC using the re-computed softmetrics.
 8. The method according to claim 7, wherein adding theadditional threshold comprises progressively increasing a number of theread thresholds until a predetermined condition is met.
 9. The methodaccording to claim 1, wherein reading the data from a first group of theanalog memory cells further comprises estimating interference caused tothe first group by a second group of the analog memory cells andcanceling the estimated interference.
 10. The method according to claim9, wherein canceling the estimated interference comprises modifying thesoft metrics associated with the first group responsively to theestimated interference.
 11. The method according to claim 9, andcomprising, upon failing to decode the ECC in the first group, selectingwhether to perform one of: re-reading the data in the second group, soas to re-estimate and cancel the interference; re-estimating theinterference by reading the data in a third group of the memory cells;and adding one or more additional read thresholds and re-reading thedata in the first group using the additional read thresholds.
 12. Themethod according to claim 1, wherein computing the soft metricscomprises normalizing the soft metrics so as not to depend on a numberof the read thresholds.
 13. The method according to claim 1, whereinperforming the multiple read operations comprises positioning themultiple read thresholds at non-uniform intervals with respect to oneanother.
 14. The method according to claim 1, wherein the analog outputvalues associated with each memory state are distributed in a respectivestatistical distribution, and wherein reading the stored data comprisespositioning the at least two of the read thresholds about a midpointbetween respective statistical distributions of the analog output valuesassociated with the memory states represented by the adjacent analogvalue regions.
 15. The method according to claim 1, wherein two or moreof the comparison results for a given analog memory cell areinconsistent with one another.
 16. A data storage apparatus, comprising:an interface, which is operative to communicate with a memory thatincludes a plurality of analog memory cells; and a memory signalprocessor (MSP), which is connected to the interface and is coupledconfigured to store data, which is encoded with an Error Correction Code(ECC), in the analog memory cells by writing respective input analogvalues that program the analog memory cells to a set of memory states,to read the stored data multiple times from each analog memory cell byperforming multiple read operations that compare analog output values ofthe analog memory cells to different, respective read thresholds so asto produce multiple comparison results for each of the analog memorycells, wherein the analog output values associated with each memorystate lie in a respective analog value region, wherein analog valueregions are separated by one or more boundary regions, and wherein atleast two of the read thresholds are positioned in a boundary regionbetween a pair of adjacent ones of the analog value regions, to computesoft metrics responsively to the multiple comparison results, and todecode the ECC using the soft metrics, so as to extract the data storedin the analog memory cells; wherein a plurality of the memory cellsstores two or more bits of the data; wherein the MSP is furtherconfigured to: read the two or more data bits in respective two or moredecoding stages, and modify a soft metric of a first bit read in a firstdecoding stage dependent upon a value of a second bit read in a seconddecoding stage that precedes the first decoding stage; and wherein tomodify the soft metric, the MSP is further configured to conditionallyinvert the soft metric of the first bit depending on the value of thesecond bit.
 17. The apparatus according to claim 16, wherein each of theanalog memory cells stores one or more bits of the data, and whereineach of the soft metrics corresponds to one of the bits.
 18. Theapparatus according to claim 17, wherein each of at least some of theanalog memory cells stores two or more bits of the data, and wherein theMSP is coupled to read the two or more data bits in respective two ormore decoding stages, and to modify a soft metric of a first bit read ina first decoding stage responsively to a value of a second bit read in asecond decoding stage that precedes the first decoding stage.
 19. Theapparatus according to claim 18, wherein the MSP is coupled toconditionally invert the soft metric of the first bit depending on thevalue of the second bit.
 20. The apparatus according to claim 16,wherein the MSP is coupled configured to make an initial attempt todecode the ECC using an initial set of the read thresholds, such that nomore than one of the read thresholds in the initial set is positioned inany given boundary region, and to compare the analog output values tothe multiple read thresholds upon failure of the initial attempt. 21.The apparatus according to claim 16, wherein each comparison result hasone of first and second possible values, and wherein the MSP is coupledconfigured to determine respective first and second counts of thecomparison results having the first and second possible values, and tocompute the soft metrics based on the first and second counts.
 22. Theapparatus according to claim 16, wherein, upon failing to decode theECC, the MSP is coupled configured to add one or more additional readthresholds to the multiple read thresholds, to recompute the softmetrics responsively to the additional read thresholds and to decode theECC using the recomputed soft metrics.
 23. The apparatus according toclaim 22, wherein the MSP is coupled configured to progressivelyincrease a number of the read thresholds until a predetermined conditionis met.
 24. The apparatus according to claim 16, wherein the MSP iscoupled configured to estimate interference caused to a first group ofthe analog memory cells by a second group of the analog memory cells,and to cancel the estimated interference.
 25. The apparatus according toclaim 24, wherein the MSP is coupled configured to modify the softmetrics associated with the first group responsively to the estimatedinterference.
 26. The apparatus according to claim 24, wherein, uponfailing to decode the ECC in the first group, the MSP is coupledconfigured to select whether to perform one of: re-reading the data inthe second group, so as to re-estimate and cancel the interference;re-estimating the interference by reading the data in a third group ofthe memory cells; and adding one or more additional read thresholds andre-reading the data in the first group using the additional readthresholds.
 27. The apparatus according to claim 16, wherein the MSP iscoupled configured to normalize the soft metrics so as not to depend ona number of read thresholds.
 28. The apparatus according to claim 16,wherein the MSP is coupled configured to position the multiple readthresholds at non-uniform intervals with respect to one another.
 29. Theapparatus according to claim 16, wherein the analog output valuesassociated with each memory state are distributed in a respectivestatistical distribution, and wherein the MSP is coupled configured toposition the at least two of the read thresholds about a midpointbetween respective statistical distributions of the analog output valuesassociated with the memory states represented by the adjacent analogvalue regions.
 30. The apparatus according to claim 16, wherein two ormore of the comparison results for a given analog memory cell areinconsistent with one another.
 31. A data storage apparatus, comprising:a memory device, comprising: a plurality of analog memory cells, whichare configured to store data, which is encoded with an Error CorrectionCode (ECC) and written to the analog memory cells as respective analoginput values that program the analog memory cells to a set of memorystates; and reading circuitry, which is coupled to read the stored datamultiple times from each analog memory cell by performing multiple readoperations that compare output analog values of the analog memory cellsto different, respective read thresholds so as to produce multiplecomparison results for each of the analog memory cells, wherein theanalog output values associated with each memory state lie in arespective analog value region, wherein analog value regions areseparated by one or more boundary regions, and wherein at least two ofthe read thresholds are positioned in a boundary region between a pairof adjacent ones of the analog value regions, to compute soft metricsresponsively to the multiple comparison results, and to output thecomputed soft metrics; and a Memory Signal Processor (MSP) device, whichis connected to the memory device and is coupled to accept the softmetrics computed by the reading circuitry, and to decode the ECC usingthe soft metrics.
 32. A method for operating a memory, comprising:storing data, which is encoded with an Error Correction Code (ECC), in agroup of analog memory cells of the memory by writing to the analogmemory cells in the group respective analog input values; reading thedata from the analog memory cells in the group by comparing analogoutput values of the analog memory cells in the group to one or moreread thresholds, and applying ECC decoding to the read data; and upon afailure of the ECC decoding, canceling interference caused to the analogmemory cells in the group by at least one other analog memory cell, andre-decoding the ECC.
 33. A data storage apparatus, comprising: aninterface, which is operative to communicate with a memory that includesa plurality of analog memory cells; and a memory signal processor (MSP),which is connected to the interface and is coupled to store data, whichis encoded with an Error Correction Code (ECC), in a group of analogmemory cells of the memory by writing to the analog memory cells in thegroup respective analog input values, to read the data from the analogmemory cells in the group by comparing analog output values of theanalog memory cells in the group to one or more read thresholds, andapplying ECC decoding to the read data, and, upon a failure of the ECCdecoding, to cancel interference caused to the analog memory cells inthe group by at least one other analog memory cell, and to re-decode theECC.
 34. A method for reading a memory cell of a non-volatile memory,comprising: performing a first read operation of a memory cell dependentupon a first read threshold, wherein data stored in the memory cell isencoded with an Error Correction Code (ECC); performing a second readoperation of the memory cell dependent upon a second read threshold,wherein the first read threshold and the second read threshold arepositioned in a boundary region relative to two possible memory states;and determining a soft metric using the results of the first readoperation and the second read operation; modifying the soft metric byconditionally inverting the soft metric depending on a value of a databit read from another memory cell; and decoding the ECC using the softmetric to extract the data from the memory cell.
 35. The method of claim34, wherein the boundary region comprises an area of overlap betweendistributions of two memory states.
 36. The method of claim 34, furthercomprising performing an initial read operation of the non-volatilememory cell dependent upon an initial read threshold prior to the firstand second read operations.
 37. The method of claim 36, wherein thefirst read operation and the second read operation are performedresponsive to a failure of an error correction process dependent uponresults of the initial read operation.
 38. The method of claim 36,wherein the first read threshold is less than the initial readthreshold, and wherein the second threshold is greater than the initialread threshold.
 39. The method of claim 34, further comprisingdetermining an interference caused to the memory cell by at least oneother memory cell and compensating for the interference.
 40. A methodfor operating a non-volatile memory, wherein the non-volatile memoryincludes a plurality of memory cells, the method, comprising: performinga first read on a first group of the plurality of memory cells dependentupon a first read threshold, wherein data stored in the first group ofthe plurality of memory cells is encoded with an Error Correction Code(ECC); performing a second read on the first group of the plurality ofmemory cells dependent upon a second read threshold; determining atleast one soft metric dependent upon results of the first read operationand the second read operation; decoding the ECC using the at least onesoft metric; responsive to a failure to decode the ECC, performing athird read on the first group of the plurality of memory cells dependentupon a third read threshold; updating at least one soft metric dependentupon a result of the third read; wherein a of the plurality memory cellsstores two or more bits of the data; wherein performing the first readon the first group includes reading the two or more data bits of amemory cell in the first group in respective two or more decodingstages; wherein determining the soft metric includes modifying a softmetric of a first bit read in a first decoding stage dependent upon avalue of a second bit read in a second decoding stage that precedes thefirst decoding stage; and wherein modifying the at least one soft metricincludes conditionally inverting the soft metric of the first bitdependent upon the value of the second bit.
 41. The method of claim 40,wherein updating the at least one soft metric comprises determining anew soft metric dependent upon the results of the first read operationand the second read operation, and results of the third read operation.42. The method of claim 40, wherein the ECC comprises a low-densityparity-check (LDPC) code.